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Author (up) Mancini, T.; Mari, F.; Massini, A.; Melatti, I.; Tronci, E. pdf  url
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  Title Anytime system level verification via parallel random exhaustive hardware in the loop simulation Type Journal Article
  Year 2016 Publication Microprocessors and Microsystems Abbreviated Journal  
  Volume 41 Issue Pages 12-28  
  Keywords Model Checking of Hybrid Systems; Model checking driven simulation; Hardware in the loop simulation  
  Abstract Abstract System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability.  
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  Series Volume Series Issue Edition  
  ISSN 0141-9331 ISBN Medium  
  Area Expedition Conference  
  Notes Approved no  
  Call Number UNIROMA1 @ davi @ Mancini201612 Serial 59  
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